“Setup time” and “hold time” describe the timing requirements on the data input of a sequential logic element, such as a flip-flop or register, with respect to a clock input. The set-up and hold times define a window of time during which data must be stable to guarantee predictable performance over a full range of operating conditions and manufacturing tolerances. The setup time is the minimum amount of time that an input data signal must be held steady before a clock event, such as a rising or falling edge of a clock signal, in order for the state of the data signal to be reliably captured. Hold time is the minimum amount of time the input data signal should be held steady after the clock event in order for the state of the data signal to be reliably captured. A setup time violation, which is sometimes referred to as a long path problem, can be remedied by reducing the path length or reducing the clock speed. A hold time violation, which is sometimes referred to as a short path problem, can be remedied by increasing the path length or adding delay circuitry to the signal path.
Some circuit timing problems may not be discovered until late in a design flow. That is, after a circuit design has been implemented as a circuit, errors may be discovered during testing. Fixing the circuit design at this late stage may be prohibitively expensive. In an effort to address late-discovered timing problems, some designs include pipeline registers nearly “everywhere” in the circuit design, for example, at the input and output of each flip-flop. Circuits having pipeline registers at every location may be advantageous for optimizing timing but can be very costly.